Digital Circuits and SystemsHomework Assignment #5Name ____________________________Using Quartus II or an equivalent VHDL entry program model the D flip-flop shown below. Attach the simulation file.Using Quartus II or an equivalent VHDL entry program model the D flip-flop shown below. Attach the simulation file.Using Quartus II or an equivalent VHDL entry program model the J-K flip-flop shown below. Attach the simulation file.Using Quartus II or an equivalent VHDL entry program develop the text file and simulation for the circuit below. Attach the .vhd and simulation files. The group of bits 10110101 is serially shifted (right-most bit first) into an 8-bit shift register with an initial state of 11100100. After two clock pulses the register contains:(a) 01011110 (b) 10110101 (c) 01111001 (d) 00101101With a 100 kHz clock frequency eight bits can be serially entered into a shift register in:(a) 80 (s (b) 8 (s (c) 80 ms (d) 10 (sFor a 10-bit serial-in/serial-out shift register determine Data out for the Data in and clock waveforms shown below. Assume that the register is initially cleared.Using Quartus II or an equivalent VHDL entry program develop the text file and simulation for the shift register specified in Problem 7. Verify the timing diagram shown in Problem 7. Attach the .vhd and simulation files. Using Quartus II or an equivalent VHDL entry program develop the text file and simulation for the 74LS194A universal bi-directional shift register. Attach the .vhd and simulation files. In your own words explain the purpose of concatenation in a VHDL signal assignment.ECET-230 Homework Assignment #5 Page 2 of 3Data outCLKD SRG 10 CData inCLKData inData out
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